Modern integrated circuits have billions of discrete elements (e.g. transistors). Terminals of the discrete elements are connected by multi-level wiring. The wiring is one of the critical elements of the integrated circuits determining an upper limit of clock frequencies of the integrated circuits. The wiring has to be designed in a way that it enables error free propagation of electrical signals synchronized with the clock frequency. This means that electrical signals have to be received at receiving terminals within a time window in a tact interval. The receipt of electrical signals has to be error free. As usual it requires not only timely receiving of the electrical signals at the receiving terminals but also satisfying a required slew rate of the electrical signals at the receiving terminals.
Modern digital circuitry has tolerances for error free propagation of electrical signals in the picosecond range. The problem of finding an appropriate wiring topology is complicated by the need to design interconnect lines and the driving cells generating signals in the interconnect lines complying with the design rules. In a case when an interconnect line connects many sink cells to a driver cells an approach based on straightforward increase in a driving strength of the driver cell and a current loading capacity of the interconnect line can be counterproductive. For instance, a required cross-section of the interconnect line can substantially exceed the cross-section of the metallization wires in the metallization layer comprising the interconnect line and/or the driver cell might need to have very big transistors of the output cascade in order to provide required rising and/or falling slew rate of a signal generated at input terminals of the sink cells. In order to avoid big topological disparity between other elements of the design and the driver cell and/or interconnect line and/or in order to generate layouts of the driver cell and/or interconnect line complying with the design rules the interconnected lines are shunted by the shunt lines. The shunt lines can be connected to the same driver cells as the respective interconnect lines, or they can be connected to additional/auxiliary driver cells. When the shunt lines are employed for facilitating of the propagation of the electrical signals in the respective interconnect lines, not only propagation of electrical signals in the wiring as such (e.g. interconnect lines) has to be taken into account but parasitic electromagnetic interactions of electrical signals propagating in adjacent wires (e.g. interconnect line and its shunt line) have to be taken into account as well. The last but not least problem is that a complete performance of the wiring can be calculated only when the wiring topology is completely generated. As a consequence a process of generation of the wiring topology is performed as usual just using simple design rules being primarily derived from constraints of an integrated circuit manufacturing process. Thus there is a need to improve the process of the generation of the wiring topology in a way that information related to the electrical performance of the wiring is taken into account during generation of the wiring topology resulting in a solution meeting the requirements of electrical performance of the wiring.